FIG. 1a shows a standard prior art DAC current source circuit 10 effective for active to non-active mode switching in the range of 100 Megahertz. The prior art DAC current source circuit 10 includes first, second, and third p-channel CMOS transistors, respectively transistors 12, 14, and 16. For convenience, transistors 12, 14, and 16 are additionally referred to as respective transistors Q1, Q2, and Q3. These three transistors are connected to a central node 20. More particularly, transistor 12 (i.e., Q1) is connected to Vcc, the DC voltage source, and to node 20, while driven at its gate by a COMP signal. Transistor 14 (i.e., Q2) is connected between node 20 and ground, receiving the input signal at its gate. Finally, transistor 16 (i.e., Q3) is connected between node 20 and an output connection 24, while being driven at its gate by a reference signal, Vref.
DAC current source circuit 10 in FIG. 1a is unfortunately hampered by a long output settling time. This is caused by the gate to source capacitance of transistor 14 (i.e., Q2), as emphasized by the parasitic capacitance illustration in FIG. 2. The gate to source capacitance of transistor 14 is represented by a parasitic capacitor 32 including capacitor C2 and leads connecting capacitor C2 to the gate and source of transistor 14.
Further, the DAC current source circuit 10 is subject to undesired current spiking at output connection 24, i.e., OUTPUT, when the INPUT connection to transistor 14 is switched. This current spiking effect is caused by the gate to source capacitance of transistor 14, which is represented by a parasitic capacitor circuit 32 including capacitor C2 and leads for connecting capacitor C1 to the drain and source of transistor 14. As can be seen in FIG. 2, transistor 14 is connected to node 20 of DAC current source circuit 10. When the input signal at the gate of transistor Q2 switches, the parasitic capacitance represented by parasitic capacitor C2 will cause the voltage level at node 20 to rise rapidly. This rise in voltage level is accompanied by significant and undesired current spiking at the output connection 24 during transition times.
With input signal switching at the gate of transistor 14 in DAC current source circuit 10 in FIGS. 1a and 2, the voltage at node 20 is subject to considerable change accompanied by undesired current spiking, as noted above. The effect of the voltage change at node 20 will be applied through the parasitic capacitances represented by parasitic capacitors C1 and C3. This in turn will affect the bias voltages COMP and Vref. With these bias voltages changing, the DAC current source will not provide the desired constant current source at transition times. Moreover, at higher speeds (i.e., frequencies), increased noise levels and current spiking are not unlikely.
FIG. 1b shows the circuitry of FIG. 1a further including a driver circuit 23, according to the prior art, for producing the input COMP signal for DAC current source circuit 10. Driver circuit 23 includes an operational amplifier or opamp 24' connected to the gate of a transistor 25 comparable to transistor 12 in basic characteristics of DC and steady state operation. Opamp 24' has plus and minus inputs, the minus input being connected to input Vref and the plus input being connected to node 26. This connection scheme ensures that opamp output signal COMP will be negative when Vref changes in a positive direction and negative when Vref changes in a positive direction. During steady state, the output of opamp 24', i.e., COMP, will be steady, because Rset, the voltage value at node 26, will follow the value of Vref.
Transistor 25 is typically a p-channel field effect transistor connected at its source to Vcc. Driver circuit 23 further includes a resistor 27 connected to a node 26 at the drain of transistor 25. The resistance of resistor 27 is effective for determining the amount of electric current flowing between the source and drain connections of transistor 25 and through resistor 27 itself. As the characteristics of transistors 25 and 12 are the same and the resistance of resistor 27 and the conducting one of transistors 14 and 16 are the same, the conductive current Ic through resistor 27 will be the same as the conductive current Ic passing through the conducting one of transistors 14 and 16.
According to one implementation of the prior art circuitry shown in FIGS. 1a, 1b, and 2, is shown in the diagrams of FIGS. 5b and 5d which show output waveforms for a DAC current source circuit according to the prior art producing non-ideal pulses having considerable undesired ringing effects which are particularly pronounced immediately after a transition between low and high pulse amplitude values or between high and low pulse amplitude values.
It is further well-known according to the prior art, that DAC current sources can be interconnected to form a digital to analog converter 29 as shown in FIG. 1c. The digital to analog converter or DAC 29 in this case includes a plurality of current source circuits 10 each having an input and an output connection. The DAC 29 shown is effective for converting a portion of a byte of digital bits into an analog equivalent current. The complete digital byte includes respective bits A7-A0, beginning with the most significant bit (MSB) and ending with the least significant bit (LSB). The lowest significant bit A0 is applied to the input of a single DAC current source 10a. The next significant bit A1 is applied to the respective inputs of first and second DAC current sources, respectively 10b(1) and 10b(2). This scheme continues until the most significant bit input is applied to the respective inputs of first through one hundred twenty-eighth DAC current sources, respectively 10h(1) through 10h(128). The analog output node 24 of the digital to analog converter 29 is connected to each of DAC current sources 10a(1), 10b(1), 10b(2), 10c(1) . . . 10c(4), 10d(1) . . . 10d(8), 10e(1) . . . 10e(16), 10f(1) . . . 10f(32), 10g(1) . . . 10g(64), 10h(1) . . . and 10h(128). According to this arrangement of the prior art, if the value of a particular input bit is one, the first current amount provided by a first one of DAC current sources is enhanced by any DAC current sources following after the first current source. For example, if the most significant bit A7 is 1, the initial current amount produced by DAC current source 10h(1) is multiplied by a factor of two to the seventh power (i.e., 128) by the contributions of the succeeding DAC current sources 10h(1) through 10h(128).
It is accordingly an object of the invention to develop a high frequency current source for digital to analog conversion applications, which is not subject to the inadequacies, limitations, and problems of the prior art.
It is an object of the invention to enable fast and smooth current source switching for DAC applications effective for high speed switching from digital to analog states.
Additionally, it is an object of the invention to develop an integrated circuit, CMOS current source applicable to digital to analog conversion circuit designs.